Frequency Multiplier for Low Frequency with Noise Rejection

Figure 1 

The circuit was designed to produce a frequency multiplier for low frequency from the measurement of their signals while eliminating the noise that comes with them.

• CA3130 – a BiMOS operational amplifier that combines the advantage of both bipolar transistors and CMOS, which can be used in photodiode sensor amplifiers, peak detectors, single-supply full wave precision rectifiers, voltage regulators and followers, high input impedance comparators and wideband amplifiers, long duration timers, fast sample-hold amplifiers, and ground referenced single supply amplifiers
• 4046 – a phase locked loop CMOS logic IC used in motor speed control, FSK modulation, tone decoding, voltage-to-frequency conversion, data conditioning and synchronization, frequency discrimination, frequency multiplication and synthesis, and FM modulator and demodulator, due to its high VCO linearity, low frequency drift, low dynamic power consumption, and wide supply voltage range
• 4518 – a dual BCD counter made of MOS P-channel and N-channel enhancement mode devices in a single monolithic structure primarily used in multi-stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity due to its low input capacitance, logic edge-clocked design, 6MHz counting rate, diode protection on all inputs, capability of driving two low-power TTL loads, and internally synchronous for high internal and external speeds

Most frequency meters are designed with specifications in measuring and indicating a frequency range of 50 Hz to 100 Hz. Oftentimes, there is no precision when driving signals with low frequency. For this precise frequency to be achieved, the meter gate should have timing of 10 seconds or longer which will eventually show a precise frequency of 0.1 Hz. The timing refers to the number of indication per minute during the regulation and measurement of the circuit which is six times.

The circuit imposes a useful multiplier of frequency where the signals are transformed to regular square waves, if they contain small rise and dip timings and noise. This procedure is done before feeding the input of phase locked loop IC. It will then function as a comparator than can process signals up to 50 KHz while the use of switch S1 can turn the circuit IN or OUT. Between the VCO is a driving signal to the input of divider through R4 which will proceed to the phase comparator IC2 4046. The frequency signals will multiply from smaller than 1 Hz until given the values of the components a definite hundreds of Hertz that can be measured by any instrument.

The operation of the circuit works by the entry of pulses in the input of IC1. The fault signal produced comes from a low pass filter consisting of C5 & R3-4, which is fed to the input of VCO that starts the capturing process. Since the frequency of VCO is hindered by a divider at 100 ohms between the second input of comparator and the output of VCO, the input frequency is 100 times as it locks. The time it takes for the input signal to be locked consists of seconds until the signal is minimized.

Figure 2 

The theory of frequency multiplier used in this circuit may be applied in radio receiver or transmitter circuits to synchronize onto the transmission carrier frequency to permit uncomplicated demodulation. It can also be used in engines with low rotation and measurement of biological signals.

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