Programmable Frequency Divider Circuit

Figure 1 

The circuit was designed to divide the frequency of a TTL compatible square wave signal which can be programmed with the use of three 7490 to perform the required operation.

• 7430 – an 8-input NAND gate that contains a single gate which performs the logic NAND function on a dual in-line package
• 7490 – a monolithic BCD counter that contains four master-slave flip flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five with a gated zero reset and gated set-to-nine inputs for use in BCD nine’s complement applications
• 7400 – a quadruple 2-input NAND gate employing Transistor-Transistor Logic (TTL) to achieve high speed at moderate power dissipation and provide the basic functions used in the implementation of digital integrated circuit systems due to its low output impedance, minimal variation in switching times with temperature, high noise immunity, and good capacitive drive capability

The frequency of a TTL compatible square wave signal is divided by a factor from 0 to 999 which makes the circuit very useful. It consists of a few NAND gates and three decade counters IC1 to IC3 using a single integrated circuit with model 7490. They are in a cascaded format where the input signal is counted. The output of IC4 will become low when the desired and count reaches all the inputs of IC1-3, causing the input of IC4 to become high. This action will trigger the monostable that is formed by the IC5B and IC5C that will provide the output pulse. The three counters and the count will reset when the output of IC5A becomes high.

The binary coded decimal (BCD) equivalent of the required division ratio needs to be worked out in order to program the counter on the initial stage. The +5 V supply is connected to the unused inputs of IC4 through the 1K ohm resistor. The division ratio of the circuit is 569 and will not divide by 777 since it requires 9 inputs of IC4 while only 8 inputs are available.

Figure 2 

The programmable frequency divider may be used in a number of electronic applications such as fax or modem interface used in a personal computer system that is capable of selecting a large number of clock frequencies for driving internal Universal Asynchronous Receiver/Transmitter (UART). In all the applications related to this circuit, the most important feature that they offer is digital timing and frequency division since they are easily cascadable giving limitless possibilities to timing delays. Other types of programmable frequency divider are used in scope triggering, in working with ECL circuits as an essential lab tool, SONET clock generator, systems clock simulation, PRBS/BERT synchronization, testing high-speed serial links, low jitter NECL clock source, and laser pump synchronization.

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