Amazon's best-selling FPGA book, "FPGA Simulation: A Complete Step by Step Guide", shows you how to find and fix bugs before you go into the lab.
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For the past several months we've been looking into what it takes to write good RTL code. We've looked at how to write register-driven RTL, how to write combinatorial processes, and how to write state machines.
State machines are so common that there are tools devoted to creating them by drawing circles and arts. There are simulators that will recognize your state machine and animate it to help you debug it. There are even synthesis tools that will add error correcting logic to your state machines so that it can recover from the single event upsets that can happen at high altitude or in electrically noisy environments.
State machines are a foundation of digital design. Eventually we all reach the point where we need to control our digital algorithm, and we almost always turn to a state machine to do the job.
When we use procedural code to create combinatorial logic, we need to be careful to define all the paths through the logic. If we don't, we can unintentionally create latches in our design. These latches can screw up our simulation results, timing results, and area results.
While it is tempting to write RTL and let the synthesis tool take over, this isn't the best way to get the results we want. In this article, we'll learn how to create complex combinatorial code in process blocks and always blocks. We'll look at a example where our coding style creates a 10x improvement in area results.
Last month we put the 'R' into RTL by discussing registers and how to create them in Verilog and VHDL. We learned how to create resets, both synchronous and asynchronous, clock enables, and even...clock enables with resets. But, creating registers is only part of the story when it comes to digital design.
Many years ago, when I was a young man and the Boston Red Sox had just lost the 1986 world series, controversy stalked the land of hardward development. A new technology called Register Transfer Language or RTL...
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