Maximize Power-Supply Performance and Minimize Emissions
General Layout Guidelines
1. Minimize the trace loop area for the input capacitor (C3), inductor (L1), and output capacitor (C2).
2. Place the BIAS output capacitor (C4) as close to pin 13 (BIAS) and pin 14 (GND) as possible without any vias between the pins and the capacitor. This is the analog supply for the IC; any inductance on this connection will increase noise on the BIAS supply which can, in turn, increase jitter on the LX output.
3. A shorter trace is better than a wider trace.
Optimizing the AC-DC Current Path
To minimize emissions, the layout on the passive components of the MAX16903/MAX16904 is critical. The paths where there are current-step changes are considered the AC-current paths and they can be seen by eliminating the paths where current flows on both the ON and OFF parts of the switching cycle. The paths that have current flowing through them during the ON and OFF cycles are considered the DC-current paths.
- AC Current Path
The MAX16903 synchronous DC-DC converter has three passive components (C2, C3, and L1) directly in the switching current path. These three components have the most impact on emissions and device performance. Figures 1 and 2 show the switching current path during the ON and OFF cycles; Figure 3 shows the difference between these two current paths where the highest di/dt occurs. Optimizing the layout of component C3 is the highest priority, followed by optimizing for L1 and C2.
- Boost AC Current Path
The MAX16903/MAX16904 DC-DC converter uses a high-side DMOS device which requires a 5V supply voltage above the LX pin (the source of the DMOS). To generate this voltage a boost capacitor is connected between the LX and BST pins (Figure 4). During the OFF cycle of the DMOS, the boost capacitor (C1) is charged from the 5V BIAS regulator. The BIAS output is also used to supply the error amplifiers. It is, therefore, important that BIAS remain as quiet as possible to remove excess noise negatively influencing the error-amplifier circuitry. The best way to accomplish this is to minimize the inductance between the connection to C4 and the MAX16903/MAX16904. Consequently, place C4 as close as possible to pin 14 (GND) and pin 13 (BIAS) without adding any vias.