Design Articles

The clock management tiles (CMT) in the Virtex-6 devices each contain two MMCMs. One of the most powerful features of the MMCM is its ability to dynamically reconfigure the phase, duty cycle, and divide values of the clock outputs. This application note describes the information necessary to reconfigure the MMCM and provides a reference design that implements all of the algorithms covered.

Reconfiguration is performed through the MMCM DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM clock outputs while the design is running. Frequency, phase, and duty cycle can all be changed dynamically. To properly reconfigure the MMCM, it must be initially set up with integer divider values, and fine phase shifting must not be enabled. Fractional dividers and the fine phase shifter are not supported for reconfiguration.

The MMCM Configuration Bit Groups and MMCM DRP Registers sections presents the configuration bits as five bit groups, provides an overview of their usage, and details the configuration bit locations as registers. This information is not necessary to use the DRP reference design; it is intended to give an overview of the internal MMCM attributes that must be changed along with their register locations. Specific information on how the attributes are calculated is provided through the reference design. The reference design functionality and use are explained in the Reference Design and Using the Reference Design sections.