Dave Vandenbout

XESS Corp. - Founder


Focused on open-source FPGA hardware & software.


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Technical Article: What’s in a Name?

September 24, 2012

When you’re writing your HDL code, what consideration should be top-of-mind? Creating a good hierarchy? Maintaining a synchronous design? Registering inputs and outputs? I’ll suggest a more basic concern: finding good names for stuff. Think for a moment what your HDL coding life would look like if…

Technical Article: State Machine Heretic

April 16, 2012

Like many of you, it’s been drilled into me by the Reuse Methodology Manual to write my state machines in VHDL as a pair of processes: a combinatorial process to compute the next state from the inputs and current state, and a sequential process to update the current state with the next state.

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