HIRAL NANDU
Pursuing MS in Computer Engineering
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Projects Post: Line Follower
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March 20, 2011
Mechatronics (JAVA): Fall 2010. Deviced a line follower with obstacle detector and optimized the speed of the same.
Projects Post: Shared Multiprocessor Simulator
March 20, 2011
Architecture of parallel computers ©: Fall 2010. Implemented a trace driven Shared Multiprocessor Simulator to study the functionality and performance of caches and coherence protocols like MSI, MESI and MOESI. Parallelized primitives that occur in a doubly linked list data structure using…
Projects Post: Viterbi Decoder
March 20, 2011
ASIC Design(verilog) : Spring 2011. Currently working on the design of a Viterbi Decoder that solves a generic Hidden Markov Model(HMM) problem.
Projects Post: dynamic instruction scheduling simulator
March 20, 2011
Employed a dynamic instruction scheduling simulator using Tomasulo’s algorithm.
Projects Post: multilevel processor cache and memory hierarchy simulator
March 20, 2011
Developed a flexible multilevel processor cache and memory hierarchy simulator to study the performance of memory hierarchies.
Projects Post: branch predictor simulator
March 20, 2011
Implemented a branch predictor simulator to design Bimodal, Gshare and Hybrid predictors well suited for the SPECint95 benchmarks.
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