Introduction

Today I want to examine some of the peculiarities of digital compensators. After reading, you should have a general grasp of design issues related to digital compensators, but also some ideas of what benefits it can provide. Like all design problems, there has to be a good match…

The digital compensation posts covered all the control aspects of building a switch mode power supply, but did not cover external communication and control. This post will demonstrate how to write dsPIC I2C code, and how to talk to the dsPIC with C#.

Assumptions

I am assuming:

1. You know how…

In my simulation post I pointed out that integrating post state calculation gave better results than integrating pre state calculation, and that my dsPIC code used pre state calculation. However, a test with the dsPIC gave better results with pre state calculation. This post gives the results, and…

In the last post I demonstrated a Finite Math simulator in Haskell. It this post I have used an enhanced version of the simulator to simulate the effect of gain and sample delay on transient response.

Simulator Enhancement

The original simulator used in the last post the plant was modeled…

Most power supply designers have never used a functional language for simulation, but then most programers don’t even know what a functional language is. So why would a hardware designer go where even the programmers won’t go? Quite simply because a functional language is more expressive and easier…

I published the schematic and layout here:

http://www.proclivis.com/Publications/tabid/173/Default.aspx

If anyone uses it in a derivative work or to duplicate my results, please contribute back to this discussion or an EEWeb post.

Todd, thinking more about your question about basis for comparison. Ignoring compensator structures, my scope shots compare against a traditional voltage mode buck, both using digital techniques, with near identical hardware. A compaison with a traditional peak current control would be quite valid….

I guess from a conceptual point of view, the bench mark is state feedback with pole placement vs adding poles and zeros. I have not tried to mix peak current control with state feedback, so I can’t comment on that. My intuition is that pole placement has the advantage that it is easier to build a…

The dsPIC is sampling voltage and current with its internal ADC. Both analog feedback signals have a one pole filter between the closed loop bandwidth and the 200Khz PWM clock. The sampling is one sample per PWM cycle. The design idea is for the filter to not influence the compensation, but also…

My last post demonstrated discrete root locus design. This post will demonstrate pole placement using state space methods. The end result will be a 4X faster transient response to a load disturbance. As in past posts, all the MATLAB, simulation, and dsPIC code will be shown.

Here is a…