Ray Salemi

For the past several months we’ve been looking into what it takes to write good RTL code. We’ve looked at how to write register-driven RTL, how to write combinatorial processes, and how to write state machines.

State machines are so common that there are tools devoted to creating them by drawing circles and arts. There are simulators that will recognize your state machine and animate it to help you debug it. There are even synthesis tools that will add error correcting logic to your state machines so that…

State machines are a foundation of digital design. Eventually we all reach the point where we need to control our digital algorithm, and we almost always turn to a state machine to do the job.

When we use procedural code to create combinatorial logic, we need to be careful to define all the paths through the logic. If we don’t, we can unintentionally create latches in our design. These latches can screw up our simulation results, timing results, and area results.

I checked out the P1800-2009 LRM and you are right. Clause 4.6 clearly states that the statements must be executed in the order in which they are written. Your code is deterministic.

Still, I prefer to write code whose plain sense reading describes the behavior. I can never be sure that another…

Hmm. You’re right about the PDF. Though I didn’t change the blog post in the past two hours. Not sure how that happened. But you’re right, the first flip flop in the PDF is just a flop. No flip.

The use of the scheduling for synthesis really isn’t recommended. Most linters will complain about…

This means “If the clock is 1 and an event just happened in this timestep”

So I guess it could be rewritten as, “If the clock is ‘1’ and it just changed” then.

Or you could just say @(posedge clk) but that’s Verilog :-)

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in process blocks and always blocks. We’ll look at a example where our coding style creates a 10x…

Last month we put the ‘R’ into RTL by discussing registers and how to create them in Verilog and VHDL. We learned how to create resets, both synchronous and asynchronous, clock enables, and even…clock enables with resets. But, creating registers is only part of the story when it comes to…

Many years ago, when I was a young man and the Boston Red Sox had just lost the 1986 world series, controversy stalked the land of hardward development. A new technology called Register Transfer Language or RTL…