A symmetric, shared memory, multiprocessor system was built on an Altera/Terasic DE2 FPGA board. The processors were derived from a stack machine designed at Hiroshima University. A memory switch shares RAM between three processors and a VGA controller. The VGA controller reads memory at 25 MHz, interleaved with an aggregate rate of 25 MHz for the three processors. A minimal set of RAM read/write functions were implemented, including an atomic test-and-set function.
Full description at
http://people.ece.cornell.edu/land/courses/ece5760/DE2/Stack_cpu.html
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