Pursuing MS in Computer Engineering

HIRAL's Projects :

Full View List View

Line Follower

Mechatronics (JAVA): Fall 2010. Deviced a line follower with obstacle detector and optimized the speed of the same.
Tags: Mechatronics

Shared Multiprocessor Simulator

Architecture of parallel computers (C): Fall 2010. Implemented a trace driven Shared Multiprocessor Simulator to study the functionality and performance of caches and coherence protocols like MSI, MESI and MOESI. Parallelized primitives that occur in a doubly linked list data structure using OpenMP directives.

Viterbi Decoder

ASIC Design(verilog) : Spring 2011. Currently working on the design of a Viterbi Decoder that solves a generic Hidden Markov Model(HMM) problem.
Tags: ASIC Design,

dynamic instruction scheduling simulator

Employed a dynamic instruction scheduling simulator using Tomasulo’s algorithm.
Tags: Computer Architecture,

multilevel processor cache and memory hierarchy simulator

Developed a flexible multilevel processor cache and memory hierarchy simulator to study the performance of memory hierarchies.
Tags: Computer Architecture,

branch predictor simulator

Implemented a branch predictor simulator to design Bimodal, Gshare and Hybrid predictors well suited for the SPECint95 benchmarks.
Tags: Computer Architecture,

Low-Power Wind Vane

Tags: Embedded Design,

Drift Monitoring system

Tags: Embedded Design,

Digital Key generator

Tags: Embedded Design,
Like free stuff? Enter Here!
EEWeb Weekly Giveaway Sponsored by Mouser This Week: STMicroelectronics SPC564A-DISP Discovery+
Enter Here
Login and enter if you're already a member.
Click Here