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Two Stage Operational Transconductance Amplifier Design
To design a 2-stage, single-ended op-amp with PMOS inputs with the following design specifications.
Project DescriptionThe first stage is a differential pair with a current mirror load. The second stage is a common source amplifier. Use a simple current source with a diode-connected PMOS load as the bias circuit. Use Miller compensation and if necessary use zero cancelling resistor.
- VDD = 3.3V
- DC Gain ≥ 60 dB
- GBW = as high as possible
- Phase Margin ≥ 60 degrees
- Slew Rate: as high as possible
- Power Consumption ≤ 1.65 mW excluding bias circuit
- CL = 5 pF
- Input Voltage Swing: 0V to 1.4V
- Output Voltage Swing: 0.3V to 2.7V
- Input-referred Offset Voltage: as low as possible
- Common Mode Rejection Ratio (CMRR): as high as possible
- Power Supply Rejection Ratio (PSRR+/PSRR-): as high as possible
Use the TSMC 0.35μm process. Simulate the design over typical, fast and slow
process corners. The process corners are defined as:
- The ‘slow’ corner (slow NMOS/slow PMOS parameters, 70 °C, 3.0 V)
- The ‘fast’ corner (fast NMOS/fast PMOS parameters, 0 °C, 3.6 V)
- Typical conditions (typical parameters, 27 °C, 3.3 V)
A two-stage op-amp configuration isolates the gain and swing requirements. The 1st stage provides high gain while the second stage gives large swings.
The first stage, however, consists of a mirror pole at node 2 in the above circuit diagram. Also, the differential pairs using active current mirrors exhibit a zero located at twice the mirror pole frequency. The greater the spacing between the Gain Crossover Frequency and the Phase Crossover Frequency, the more stable the feedback system is. The above observation leads to the concept of phase margin. To improve the latter, Miller Compensation and Zero Cancelling Resistor have been used. The former moves the output pole away from the origin and moves the dominant pole towards the origin. This effect is called Pole-Splitting. The zero in the right half plane slows down the drop of the magnitude, thereby pushing the gain crossover away from the origin. To avoid this, a zero cancelling resistor with a value Rz=gm9 -1 is used. In practice, the zero can even be moved into the left half plane so as to cancel the 1st non-dominant pole.
However, the process of cancelling the non-dominant pole has 2 important drawbacks:
- If CL is unknown or variable, it is difficult to fix the value of Rz.
- Rz, typically realised by a MOS transistor in triode region, changes substantially as output voltage excursions are coupled through Cc to node 5, thereby degrading the large-signal settling response.
Slower Corner – Open Gain Loop and Phase Plot
Slow Corner – Output Swing
Slow Corner – Noise Spectrum
Fast Corner – Open Loop Gain and Phase Plot
Fast Corner – Output Swing
Fast Corner – Noise Spectrum
- Design of MOS Operational Amplifier Design by P.Gray and R.Meyer
- Design of Analog Integrated Circuits, Behzad Razavi.
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