EEWeb Member Projects: asic-design
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2‐Dimentional Mesh Network–on‐Chip Router
Posted Apr 07, 2011 By Yucheng chiuDesigned, synthesized and verified a 2‐dimensional mesh network‐on‐chip router. It consists of FIFOs and arbiters to store and forward packets. (Verilog HDL) Performed static timing analysis…Comments(0) -
Viterbi Decoder
Posted Mar 20, 2011 By HIRAL NANDUASIC Design(verilog) : Spring 2011. Currently working on the design of a Viterbi Decoder that solves a generic Hidden Markov Model(HMM) problem.Comments(0) -
BioSignal Processor (ASIC/Advance VLSI Project)
Posted Mar 17, 2011 By zubin kumarDesigned a low power (~ 1 uW) BioSignal Processor to perform FFT and time domain operations on physiological signals. RTL intensive design. Power profiling and layout done using Synopsys and…Comments(0) -
4x1 SRAM Design (VLSI project)
Posted Mar 17, 2011 By zubin kumarDesigned a 4×1 edge triggered SRAM with basic 6T SRAM cells. Layout made in Cadence 5.1, using 250 nm technology. (Fall 2009)Comments(0) -
FPGA Implementation of 32 bit RISC processor as a single cycle CPU
Posted Mar 08, 2011 By Karthik Anand NagarajanDesigned a 32 bit RISC processor with R-type, J-type and I-type instructions using the VHDL language. Worked in a team for verification and implementation on FPGA Spartan 3E kit.Comments(0) -
Design of FIFO based Interface Communicator[ ASIC design ]
Posted Mar 08, 2011 By Karthik Anand NagarajanDesigned a dual clock FIFO with depth expansion to communicate between producer and consumer using Verilog HDL.Comments(0) -
Viterbi decoder Design
Posted Mar 08, 2011 By Guru Prasanna Mohan KarthickDesigned a Viterbi decoder in 45nm technology to solve the generic Hidden Mark Model problem. This involved digital design using Verilog HDL, Simulation in Modelsim and Synthesis in Design CompilerComments(0) -
Design and RTL synthesis of DDR2 SDRAM Memory Controller [ ASIC design ]
Posted Mar 04, 2011 By Karthik Anand NagarajanDesigned and implemented a DDR2 Controller in Verilog HDL and simulating it with Denali’s DDR2 Model Implemented the design for scalar read and write operations using Cadence NC verilog. It was…Comments(2) -
“Controller ASIC design of Concept plug & play based DC-AC inverter” (Jan 2011-)
Posted Jan 29, 2011 By Vishal Guntur•Currently working on ASIC design of controller for a 10KW Photovoltaic inverter •Efficiency required > 90%, switching frequency of inverter 1MHzComments(0) -
Utterance Matcher
Posted Jan 22, 2011 By Hemanth Kantha RajuASIC was designed for an utterance matcher used in a speech recognition system. High level coding & design, hardware architecture design, verilog coding, simulation using modelsim & synthesis using…Comments(0)
