EEWeb Member Projects: computer-architecture

• Memory Disambiguation &Branch misprediction recovery

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Implemented various memory disambiguation and branch misprediction recovery techniques in a modern superscalar architecture simulator in C++
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• Functional Verification of superscalar processor

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Verified the RTL generated by Fabscalar for Register read, Execute and Write-back stage of a pipelined superscalar CPU Created a re-usable, layered testbench architecture using SystemVerilog and…
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• Register File and Register renaming

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Implemented the register file and register renaming mechanism of a modern superscalar microarchitecture in C++
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• dynamic instruction scheduling simulator

  Posted Mar 20, 2011 By HIRAL NANDU

  Employed a dynamic instruction scheduling simulator using Tomasulo’s algorithm.
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• multilevel processor cache and memory hierarchy simulator

  Posted Mar 20, 2011 By HIRAL NANDU

  Developed a flexible multilevel processor cache and memory hierarchy simulator to study the performance of memory hierarchies.
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• branch predictor simulator

  Posted Mar 20, 2011 By HIRAL NANDU

  Implemented a branch predictor simulator to design Bimodal, Gshare and Hybrid predictors well suited for the SPECint95 benchmarks.
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• Design of 32 bit pipe-lined RISC processor as a Multicycle CPU

  Posted Mar 08, 2011 By Karthik Anand Nagarajan

  Designed a 32 bit pipe-lined RISC processor using Epd which was operated at a frequency of 100Mhz. Data dependencies were resolved using Hazard Detection Unit and Forwarding Unit.
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• Cache and Memory Hierarchy Design

  Posted Mar 08, 2011 By Guru Prasanna Mohan Karthick

  Developed a flexible cache simulator which implemented L1 cache, its Victim cache and L2 cache. Analyzed the performance of various memory hierarchy configurations with varying parameters and…
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• Memory Processor Cache Simulation and Parallel Programming

  Posted Mar 08, 2011 By Guru Prasanna Mohan Karthick

  Implemented MSI, MESI and MOESI Cache Coherence protocols in C++ and analyzed the cache performance through variation of different cache configurations. Devised a modified MOESI protocol to reduce…
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• Multi level cached memory hierarchy simulator design

  Posted Jan 22, 2011 By Hemanth Kantha Raju

  A simulator was designed for multi-level cached memory hierarchy with branch prediction & dynamic scheduling of instructions in the 5-stage pipeline, using C.
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