EEWeb Member Projects: digital-circuit-design

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  Maze Solving Robot using a PIC18F2525 Microcontroller

  Posted Jul 03, 2011 By Ilya Natarius

  The goal of the project is to create a robot that will follow a black line on a white sheet of paper and solve a maze created out of those materials….
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  Efficient Yield Estimation and Optimization for a 6-T SRAM Cell

  Posted Jun 22, 2011 By Kalpana Manickavasagam

  A very important aspect of memory design is yield analysis which takes into account the performance of SRAM cells in the presence of process…
  Comments(1)
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  VLSI

  Posted Apr 07, 2011 By Joel Abraham

  Designed a 4KB SRAM with Leakage Current Suppression using Data Retention Voltage in Cadence Virtuoso.
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  12 bit Digital to Analog Converter

  Posted Mar 30, 2011 By Rushabh Mehta

  Designed a 12 bit CMOS D/A converter employing a segmented hybrid architecture consisting of two thermometer coded current steering segments of 4…
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• Viterbi decoder Design

  Posted Mar 08, 2011 By Guru Prasanna Mohan Karthick

  Designed a Viterbi decoder in 45nm technology to solve the generic Hidden Mark Model problem. This involved digital design using Verilog HDL, Simulation in Modelsim and Synthesis in Design Compiler
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• Design of an arbiter for system on chip packet routing (VLSI design)

  Posted Mar 03, 2011 By Prerak Patel

  Worked in a team of two to design, implement, debug and test the schematic and layout of a 4-bit data arbiter. The arbiter resolves bus arbitrations between two 4-bit data transmitters and prevents…
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  Auto Power Saver

  Posted Feb 02, 2011 By Kalpana Manickavasagam

  ‘SAVE POWER’ is the most often heard slogan in this era. Our model basically controls the switching on and off of the equipments like fans,…
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• “Design & layout of Parallel-in Parallel-out Universal Shift Register”(Nov-Dec’09)

  Posted Jan 29, 2011 By Vishal Guntur

  •The total cell area was 1225 µm2 (approx) with a worst case propagation delay of 0.15ns using standard 0.25 µm technology process. (Using Cadence Virtuoso)
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• “Controller ASIC design of Concept plug & play based DC-AC inverter” (Jan 2011-)

  Posted Jan 29, 2011 By Vishal Guntur

  •Currently working on ASIC design of controller for a 10KW Photovoltaic inverter •Efficiency required > 90%, switching frequency of inverter 1MHz
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• IMEC 3D IC Test Run in IMEC 3D models

  Posted Jan 22, 2011 By Hemanth Kantha Raju

  Designed the schematic and layout of Sense Amplifier, Low Swing Driver and Receiver using Cadence Virtuoso and Calibre LVS/ DRC. The voltage swing was reduced to about 0.2V to reduce the power…
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• Design of Strong-Arm Flip-Flop in 45nm CMOS technology

  Posted Jan 22, 2011 By Hemanth Kantha Raju

  A Strong-Arm flip-flop was designed using Cadence Virtuoso 2008. The flip flop was efficiently designed and optimized for low power consumption. Low power consumption of 32uW was achieved.
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