Designed two versions of fully-differential amplifier with Gain=8, Gain Error1.95V, settling t=2.49(21.6)ns, Power=13(1.8)mW, with Hspice Including Design of Amplifier Topology,…
Designed and Achieved an Energy-Efficient FPGA CLB functioned as 1×8 bit adder,2×4 bit adder or 4×4-input LUT,0.415 PJ/cycle,1.99ns critical path delay Including Topology Design,…
Performed Stochastic Analysis of Process Variation in SRAM Cell and Optimization for high Yield Rate, considering process variation in Vth and Leff of SRAM MOSFET Including…
Designed a Tunable Complex Active Driving Point Impedance from 800MHz to 3GHz with passband 10kOhm; (80dB, ripple2dB), stopband60dB, cutoff frequency +-3MHz and +-9MHz for pass- and…