EEWeb Member Projects: layout-design

• 16X16 Pipelined Wallace Tree Multiplier

  Posted Apr 07, 2011 By Yucheng chiu

  Implemented a 16X16 pipelined multiplier in schematic and layout (Virtuoso). Optimized the product of delay‐area of 32‐bit CRA with asymmetric and skewed gates Multiplier composed of…
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• 64 bit Synchronous CAM Design

  Posted Mar 08, 2011 By Guru Prasanna Mohan Karthick

  Collaborated with 2 team members and designed a 2 GHz, 8*8 Content Addressable Memory (CAM) in 45nm CMOS process. Implemented the complete physical layout of the circuit using Cadence Design…
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• System-on-Chip Data Packet Routing

  Posted Mar 03, 2011 By Jiechen Shou

  Directed by Professor Shahin, Nazarian 1 Constructed the 2-1 Arbiter to achieve fair arbitration for two 4-bit data transmitters which works well at 0.9GHz and has an area of = 5687um2…
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• “Design & layout of Parallel-in Parallel-out Universal Shift Register”(Nov-Dec’09)

  Posted Jan 29, 2011 By Vishal Guntur

  •The total cell area was 1225 µm2 (approx) with a worst case propagation delay of 0.15ns using standard 0.25 µm technology process. (Using Cadence Virtuoso)
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• 128 bit Single-port synchronous SRAM in 45nm CMOS technology

  Posted Jan 22, 2011 By Hemanth Kantha Raju

  Schematic and layout of SRAM bit cell array, decoders and clock tree were designed and optimized for low power consumption using Cadence virtuoso 2008 and Calibre LVS/DRC.
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