EEWeb Member Projects: memory

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  VLSI

  Posted Apr 07, 2011 By Joel Abraham

  Designed a 4KB SRAM with Leakage Current Suppression using Data Retention Voltage in Cadence Virtuoso.
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• SRAM System

  Posted Apr 07, 2011 By Yucheng chiu

  Implemented the Intel 2147 SRAM (4K bit) based on CMOS‐based 6T SRAM cell (Virtuoso). Used Divided Word Line (DWL) architecture to improve access time. Used Address Transition Detection (ATD)…
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  Falling Sand Game

  Posted Feb 18, 2011 By Skyler Schneider

  I created a hardware implementation of a falling sand game, inspired by the Java-coded Pyro Sand Game, which is not actually a “game” in the…
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  64 bit CAM Implementation

  Posted Feb 02, 2011 By Santosh Ramachandran

  We have designed a 3.03 GHz 64bit (8*8) Content addressable memory (CAM).
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