EEWeb Member Projects: superscalar-processor

• Memory Disambiguation &Branch misprediction recovery

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Implemented various memory disambiguation and branch misprediction recovery techniques in a modern superscalar architecture simulator in C++
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• Functional Verification of superscalar processor

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Verified the RTL generated by Fabscalar for Register read, Execute and Write-back stage of a pipelined superscalar CPU Created a re-usable, layered testbench architecture using SystemVerilog and…
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• Register File and Register renaming

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Implemented the register file and register renaming mechanism of a modern superscalar microarchitecture in C++
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• ILP Limit study

  Posted Dec 27, 2011 By Guru Prasanna Mohan Karthick

  Exercised an execution-driven superscalar processor simulator (721sim) based on Simplescalar ISA for a simple ILP limit study on SPEC2K benchmarks
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