EEWeb Member Projects: verilog
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2‐Dimentional Mesh Network–on‐Chip Router
Posted Apr 07, 2011 By Yucheng chiuDesigned, synthesized and verified a 2‐dimensional mesh network‐on‐chip router. It consists of FIFOs and arbiters to store and forward packets. (Verilog HDL) Performed static timing analysis…Comments(0) -
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Variable Length Packet Header Processor using High Performance FPGAs
Posted Mar 11, 2011 By Madhavi PrasadComments(0) -
Viterbi decoder Design
Posted Mar 08, 2011 By Guru Prasanna Mohan KarthickDesigned a Viterbi decoder in 45nm technology to solve the generic Hidden Mark Model problem. This involved digital design using Verilog HDL, Simulation in Modelsim and Synthesis in Design CompilerComments(0) -
DDR2 Controller Design Project
Posted Mar 06, 2011 By Han Lei LockDesigned a 500MHz DDR2 SDRAM memory controller using NC-Verilog and synthesized the design using Design Compiler with TSMC018 technology. Improved the speed of read/write operation with bank…Comments(0)
