EEWeb Member Projects: vlsi
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SRAM System
Posted Apr 07, 2011 By Yucheng chiuImplemented the Intel 2147 SRAM (4K bit) based on CMOS‐based 6T SRAM cell (Virtuoso). Used Divided Word Line (DWL) architecture to improve access time. Used Address Transition Detection (ATD)…Comments(0) -
Design of VLSI Circuits and Systems
Posted Mar 24, 2011 By Bo WenDesigned and Achieved an Energy-Efficient FPGA CLB functioned as 1×8 bit adder,2×4 bit adder or 4×4-input LUT,0.415 PJ/cycle,1.99ns critical path delay Including Topology Design,…Comments(1) -
Modeling of VLSI Circuits and Systems
Posted Mar 24, 2011 By Bo WenPerformed Stochastic Analysis of Process Variation in SRAM Cell and Optimization for high Yield Rate, considering process variation in Vth and Leff of SRAM MOSFET Including…Comments(0) -
Self-sustained 0.5um CMOS Process Colorimeter
Posted Mar 24, 2011 By Fangming YeFabricated BDJ structures in 0.5um CMOS process, in order to investigate failure models and to adopt suitable structure with low power consumption and high light sensitivity. Designed self-sustained…Comments(0) -
BioSignal Processor (ASIC/Advance VLSI Project)
Posted Mar 17, 2011 By zubin kumarDesigned a low power (~ 1 uW) BioSignal Processor to perform FFT and time domain operations on physiological signals. RTL intensive design. Power profiling and layout done using Synopsys and…Comments(0) -
4x1 SRAM Design (VLSI project)
Posted Mar 17, 2011 By zubin kumarDesigned a 4×1 edge triggered SRAM with basic 6T SRAM cells. Layout made in Cadence 5.1, using 250 nm technology. (Fall 2009)Comments(0) -
Digital VLSI Design Project
Posted Mar 06, 2011 By Han Lei LockDesigned a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.Comments(0) -
“Design & layout of Parallel-in Parallel-out Universal Shift Register”(Nov-Dec’09)
Posted Jan 29, 2011 By Vishal Guntur•The total cell area was 1225 µm2 (approx) with a worst case propagation delay of 0.15ns using standard 0.25 µm technology process. (Using Cadence Virtuoso)Comments(0) -
128 bit Single-port synchronous SRAM in 45nm CMOS technology
Posted Jan 22, 2011 By Hemanth Kantha RajuSchematic and layout of SRAM bit cell array, decoders and clock tree were designed and optimized for low power consumption using Cadence virtuoso 2008 and Calibre LVS/DRC.Comments(0)
