EEWeb Member Projects: vlsi-design

• Programmable Functional Unit

  Posted Aug 30, 2011 By Swapnil Christian

  Designing and implementing a programmable functional unit with 32×5 SRAM Array block, Decoders, Encoders, and Adders in .25 micron technology (In Progress)
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  2-Dimensional Arithmetic Fourier Transform Image Sensor

  Posted Jun 03, 2011 By Edwin Tan

  This is a design and fabrication of a CMOS image sensor with a non-uniform layout of pixels that enables the arithmetic Fourier Transform (AFT)…
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  Chip Gallery

  Posted May 31, 2011 By Edwin Tan

  As a VLSI designer, the proof they say, is in the tapeout. It is an amazing, but sometimes frustrating experience, to be able to take a design from…
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• Graduate Projects:

  Posted May 03, 2011 By Dhivya A Nagarajan

  MS THESIS: (Thesis Advisor: Dr. Marian K. Kazimierczuk) Design of high frequency transformer of forward PWM DC-DC converter using Area Product (Ap) and Core Geometry (Kg) methods- Jan ’10 – Nov…
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• 16X16 Pipelined Wallace Tree Multiplier

  Posted Apr 07, 2011 By Yucheng chiu

  Implemented a 16X16 pipelined multiplier in schematic and layout (Virtuoso). Optimized the product of delay‐area of 32‐bit CRA with asymmetric and skewed gates Multiplier composed of…
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• VLSI BASED PID CONTROLLER (UNDERGRAD GRADUATION PROJECT)

  Posted Mar 27, 2011 By Rahul Gaba

  Developed VLSI front end code to interface ACTEL FPGA with 230V heating system. Learned the functioning and calibration of a PID controller.
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• Three-Dimensional DRAM BISTAR Optimization

  Posted Mar 24, 2011 By Fangming Ye

  Designed delay test and BISTAR circuits for weak-short and resistive open TSVs. Implemented heuristic repair method for 3D DRAM test, based on brand and bound method. Investigated the 3DIC pre-bond…
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• Sigma Delta A/D Convertor

  Posted Mar 24, 2011 By Fangming Ye

  Designed the first order Sigma Delta A/D convertor for audio data collecting. Designed layout for Sigma Delta A/D modulator in Mentor IC and analyzed in Hspice. Simulated Sigma Delta converter in…
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• 64 bit Synchronous CAM Design

  Posted Mar 08, 2011 By Guru Prasanna Mohan Karthick

  Collaborated with 2 team members and designed a 2 GHz, 8*8 Content Addressable Memory (CAM) in 45nm CMOS process. Implemented the complete physical layout of the circuit using Cadence Design…
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  64 bit CAM Implementation

  Posted Feb 02, 2011 By Santosh Ramachandran

  We have designed a 3.03 GHz 64bit (8*8) Content addressable memory (CAM).
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