Interview with Alok Sanghavi

Featured Engineer

Alok Sanghavi

Alok Sanghavi - Technical Marketing Engineer with Jasper Design Automation

What are your favorite software tools that you use?

I’ve been a design and verification engineer for the majority of my career. I’ve used most of the software tools out there for SoC design and debug such as simulators, synthesis and linting tools as well as formal verification tools. To pick a favorite out of the lot is not an easy job but I can say that the most bang for the buck I’ve found in designing and verifying SoCs is formal verification a.k.a property checking. With formal verification, one could exhaustively verify whether a design scenario could occur without running hundreds if not thousands of random simulations. Just as HDL languages changed the way chips were designed, formal property checking is changing the way chips are verified. It’s one of the reasons I currently work in the formal space now at Jasper, helping engineers adopt the ideal formal verification methodology best suited for their designs.

What is the hardest/trickiest bug you have ever fixed?

I was working on a SoC design where a scenario (frames dropping and chip not recovering from a specific state) not even thought out in the architectural spec for my block surfaced after the chip went into production. Even when the bug was identified, the fix was not straightforward as we were not sure what additional bugs it could introduce or that the fix would work in the long run. I had to use a combination of simulation and emulation techniques to first narrow down the bug to specific areas in the design and then formal to exhaustively verify whether the fix would not introduce additional bugs. Only with property checking could I confidently say that the fix would work for all possible scenarios. The validation team then verified the fix by running simulation over the next few weeks and no intermittent or corner-case bug was found, which confirmed that the fix worked.

What is on your bookshelf?

Other than books on digital design: Liar’s Poker, The Big Short, and Doing What Matters. Clifford Cummings’ papers and Applied Formal Verification never leave my bookshelf.

Do you have any tricks up your sleeve? (special way to analyze circuits, special process you use to make something, etc.)

Designing high-quality RTL comes not just by the designer’s experience and understanding of the spec, but also by the tools and methodologies used. I realized early on that using formal property checking to verify my designs provided significant benefits. Even though using formal wasn’t mandatory in our team, I could confidently say that my designs were 100% verified only after running formal, no matter how many tests were run before. Wherever I have worked, I have been able to use this unique technology repeatedly to create high-quality designs and get more people to appreciate its usefulness.

What has been your favorite project?

My favorite project was a LCD panel chip where I was part of a 3 member team designing the entire interface to control LVDS data streams going in and out of the chip to the LCD panel. It was the first such chip for our team, and was an extremely challenging and fun project as the customer requirements used to change right in the middle of the project as would the architectural spec. We had many late and sleepless nights over the course of the project. It was a great learning experience and especially lots of fun since we had to test the chip by connecting to huge LCD panels (they had just come out) and play XBOX and PS3 all day to conduct performance testing.

Do you have any note-worthy engineering experiences? (blowing up things, getting shocked, etc.)

Back in graduate school, I had no idea how to prepare for my first job interview. So I took an entire circuit board with a 128-bit encryption algorithm implemented on it and showed it to the interviewer (and my future manager). I was quite proud of what I had done even though I ended up blowing the board during the interview! I was glad I showed the project in working state before disaster struck.

I became pretty good at establishing processes and methodologies. When linting was still new, I led initiatives across ATI (where I worked) to implement and adopt linting, all the way from weeding through thousands of linting rules and finding bugs in the tool, to mentoring other teams so they could grasp its significance and subsequently increase design productivity.

I coordinated the Jasper User’s Group meeting last year that had numerous user as well as engineering presentations where people shared their experiences on formal verification. The conference attracted more than 70 attendees and was a huge success.

What are you currently working on?

Currently I am working to educate and support design and verification engineers using and deploying formal verification technology as well as driving the next-generation of formal solutions. I am working with various customers to share their experiences on formal verification at the Design Automation Conference coming up in June 2011. I am also creating product datasheets as well as other technical collateral, which will help people understand and use Jasper’s products.

What direction do you see your business heading in the next few years?

Formal verification is getting extremely critical not just for functional verification but also during the architecture, RTL design and post-silicon validation phases. It is hard to ignore formal with ever-increasing design complexities and the need for all-in-one devices such as smartphones, computers and video game consoles with on-demand high-definition video-streaming capabilities. One area where I see significant use of formal in the near future is in post-silicon validation to isolate and fix bugs where the cost of re-spins is too big to ignore. We have had customers use formal to identify and fix post-silicon bugs and gain increased confidence in their designs prior to production. We are also seeing more and more customers use Jasper not only for formal proofs but also for other applications such as architectural verification, RTL development, low-power verification, design and IP re-use and protocol certification. Formal property checking is strongly poised to be the de-facto sign-off tool in the design and verification process in the next few years.

What challenges do you foresee in our industry?

Formal is “no longer just a verification technology.” Today’s designers and verification teams are harnessing these powerful tools early, and continuing to put them to work at every stage of the design cycle. The challenge is whether formal can push the envelope and be handed to every designer and verifier just as the top semiconductor companies are doing today with Jasper’s formal solution. The challenge will be not arguing over whether formal is part of every verification methodology but over choosing the optimum formal methodology. I definitely foresee more and more people adopting and using property checking in the near future to design and verify their solutions.