Interview with Dr. Samir Chaudhry

Featured Engineer

Dr. Samir Chaudhry

Dr. Samir Chaudhry - Director, Design Enablement at TowerJazz

What are your favorite hardware tools that you use?

As the director of the modeling and characterization group for the TowerJazz, my team is tasked to deliver compact models for active and passive devices ranging in voltage from mV to 700V, and in frequency ranging from DC to 100GHz. We have found that a wide variety of instrumentation is essential in enabling us to deliver accurate models, and as such we have invested heavily in building up our lab:

Basic DC/CV measurements: We use the Agilent 4156C with an Agilent A41501B expander for our IV sweeps. For high-voltage high-current devices, self-heating can corrupt the parametric measurements and we rely on the Diva D225EP to generate pulses down to nano-second durations to get accurate data for compact model generation.

RF & Noise Characterization: The s-parameter measurement system that we use is Agilent’s E8361C 10 MHz to 67 GHz. For RF Noise we have invested in the Maury Microwave 8 to 50 GHz system which includes the MT984AU01 8-50 GHz USB Tuner and MT7553B 50GHz Auto Down-converter. Flicker noise measurements can easily be corrupted, and we have found that the BTA9812A Noise Analyzer in conjunction with the HP35670A Dynamic Signal Analyzer gives stable and repeatable data for MOSFETs, SiGe NPNs, and poly and well resistors

Large-signal: The Focus Microwaves source and loadpull tuner iCCMT-708 (0.8-6.5GHz) with tuneable pre-match for on-wafer measurement enables us to generate load-pull contours, power and IV sweeps at Gammas as high as 0.92 and has been sufficient for most of cellular and WiFi characterization needs on SiGe NPN power cells.

What are your favorite software tools that you use?

On the design environment front, we validate our PDKs with Cadence’s analog design environment. Mentor’s Calibre is our sign-off design rule checking tool for customer tape-ins. We are also part of the iPDK alliance that is enabling common standards for foundry PDK development.

We mainly use Agilent’s IC-CAP for compact model extraction. Over the years we have built our own model extraction capabilities for models such as BSIM, PSP, and MM20 for MOSFET devices. For SiGe NPNs compact model extraction, we have relied on XMOD Technologies’ HiCUM toolkit add-on for IC-CAP. In addition, we extensively use “home-brew” Matlab scripts to automate our de-embedding and model extraction techniques for passive devices such as inductors and varactors.

What is the hardest/trickiest bug you have ever fixed?

Actually, it was my Ph.D. advisor Dr. Mark Law at the University of Florida, who helped me with Finite-element simulations that were being used to analyze wafer-bow measurements, which consistently showed a convex wafer bow when p-epi structures were grown on p+ starting material. The simulations were getting the magnitude of the bow correct, but predicted a concave bow. After over eight weeks of analysis, we discovered that there were two equally stable “lowest-energy” system states; one convex and one concave (think of metallic plate that can be “popped” up or down and remains in that state). If a slightly convex initial condition was provided to the simulation system, the simulations would converge correctly to the correct convex wafer-bow. I am convinced that I would have graduated eight weeks earlier, had the simple solution to the vexing problem been discovered earlier.

What is on your bookshelf?

Topgrading by Bradford Smart. This is a primer on how best to invest in Human Capital, beginning with hiring the right person and then developing the talent. As a manager, I have found it extremely useful in building a team that is truly outstanding.

Do you have any tricks up your sleeve? (special way to analyze circuits, special process you use to make something, etc.)

I owe this to Robert Milkovits, TowerJazz’s PDK architect. IC designers using the Cadence Analog Design Environment can save significant time and effort by using the inherited connections flow. Several foundry design kits support this flow (instead of implicit node definitions via CDF parameters) for bulk domain definition. Inherited connections offer several advantages as part of hierarchical, multi domain, and mixed-signal design. When inherited connections are used, the default bulk node is predefined (e.g. “sub” or “pwell” for devices that sit over P-substrate and “vdd” for devices over nwell). If a custom node (e.g. “pll_sub”) needs to be defined for a device, follow these guidelines:

Access the instance or symbol Edit Object Properties window, generally done through the bind key q

Click on the Add CDF button to launch the Set Property window

Under the Name text field type the name of the inherited bulk property. Select the netSet Type and assign the desired name (e.g. “pll_sub”) under the Value text field

What has been your favorite project?

I really enjoyed working on monte-carlo statistical modeling for SiGe BiCMOS technologies. The unique correlations between process parameters and the device electrical parameters required developing 1st principles based mapping equations. The statistical data from the fab gave unique insights on device behavior. As an example, the correlation between the CMOS device and poly-resistors allowed me to separate the channel-length variation for MOSFET between the perturbations of the physical gate length and source/drain lateral doping. It was gratifying to release a model that showed a good match between what was simulated and what our fab was actually producing.

Do you have any note-worthy engineering experiences? (blowing up things, getting shocked, etc.)

When I was working on my PhD, all the graduate students were strictly instructed by our campus fab supervisor to never to leave the clean-room furnace unattended. While working on anneal experiments, I often found myself working late into the night. One night, while working with the furnace, I realized that I needed to use the restroom urgently. Unfortunately, no one else was in the lab, so I felt compelled not to leave the furnace unattended even though I had been working almost non stop for 12 hours. The next day, our supervisor overheard me talking with my colleagues who were very amused by my plight. He gruffly ordered me to meet with him. I was so worried that something had happened to the furnace. Out of earshot of my colleagues, the supervisor gently explained to me that it was okay to leave the lab unattended for a few minutes to answer the call of nature. He also told me that he was very impressed with my dedication to following the protocols. I learned a valuable lesson that day – that bathroom breaks are as essential to good research as expensive equipment!

What are you currently working on?

We are expanding our statistical loop closure work. Essentially, this involves using an expanded set of process-control-monitoring statistical data and evaluating the correlations between various classes of devices. As an example, the poly-cd impacts both the MOSFETs and the poly-resistors. We are building on the Backward Propagation of Variance (BPV) work [1] done by Collin McAndrew at Freescale, to accurately separate out the various components of channel length variations in the MOSFET: poly-cd and source/drain implant related. With a careful and correct formulation, this technique has allowed us to not only accurately capture the spread in electrical parameters, but also model the correlations between the electrical behaviors across devices. Both these are essential in generating accurate monte-carlo statistical models.

What direction do you see your business heading in the next few years?

The Foundry space is split into two dominant segments: the Digital Foundry and the Specialty Foundry. The Digital Foundry leverages a large capital investment into relatively standardized technology that serves a large set of customers in a uniform way and is primarily focused on scaling CMOS. This segment of the industry will experience steady growth. The Specialty Foundry (such as my employer, TowerJazz) leverages engineering service together with a more modest capital investment to serve smaller but more custom markets such as those of RF, analog, and power. This segment of the industry will continue to carve a bigger niche for itself, leveraging device innovations at more mature CMOS nodes. Specialty foundries will continue to see significant design activity at the 130, 180 and even the 350nm process technology nodes.

What challenges do you foresee in our industry?

Efficient inventory management by IC manufacturers and the corresponding capacity management by foundries will be critical for the semiconductor industry. As has always been the case, investing wisely in process technology and capacity will separate the leaders from the followers.

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