Interview with Roshan Baliga

Featured Engineer

Roshan Baliga

Roshan Baliga - Atheros

What are your favorite hardware tools that you use?

Oscilloscopes and logic analyzers are my favorite hardware tools which I have extensively used to debug issues in hardware. Spectrum analyzers have also proven to be invaluable in debuging RF issues.

What are your favorite software tools that you use?

Matlab and Simulink are among my favorite software tools. I find myself using the Signal Processing and Communications toolbox the most.

I also loved working with System Canvas which was a tool we used for designing the physical layer of a wired home networking technology. Another software tool that I use frequently is Wireshark which is a network protocol analyzer.

What is the hardest/trickiest bug you have ever fixed?

The trickiest bug I had encountered was in the timing loop of a DVB-S demodulator that we were developing. This would cause the demodulator to lose lock after a few hours though it was designed to remain locked over a period of several days. The issue was then traced back to the RTL implementation of the loop filter where an incorrect approximation of the actual expression was used.

What is on your bookshelf?

Network Algorithmics by George Varghese, Principles of Communications Engineering by Wozencraft & Jacobs, Digital Signal Processing by Proakis & Manolakis, Computer Architecture by Hennessy & Paterson are some of the technical books on my book shelf. A large section of my bookshelf is dedicated to autobiographies of people from all walks of life. I am also fascinated by the working of the human brain and have a couple of books by Ramachandran on the subject

What has been your favorite project?

I have been fortunate enough to work on some great projects in my career – 802.11a/g PHY, DVB-S demodulator, MoCA PHY and more recently hybrid networks. Each one of these projects have been special in their own way and I have thoroughly enjoyed working on every one of them. The 802.11a PHY implementation holds a special place because it was the first major project I worked on and delivering a working solution was one of the highs of my professional life.

In regard to the 802.11a PHY you worked on, do you find that IEEE specs for protocols like this are very straight forward, with easy implementation, or are there a lot of details left to be determined by the one implementing it?

The IEEE specifications for the PHY describe the basic transmitter blocks and RF specifications in some detail. The implementation details are not specified, and the challenge is in picking optimal architectures for various blocks both in terms of complexity as well as power. The PHY design starts with a floating point Matlab model which is used to validate the performance of the algorithms. Each of the Matlab blocks is then mapped to a architecture that is suitable for implementation in hardware and this is used to build a bit exact fixed point C mode. The fixed point model is then used to generate test vectors for validating the RTL which can then be targeted to either an ASIC or an FPGA. The entire cycle from the Matlab floating point model to a fully verified RTL implementation took about 60 man months.

Do you have any note-worthy engineering experiences?

I once had to travel to a customer’s site to demonstrate an algorithm I had developed for determining the optimal placement of wireless repeaters. Unknown to me the customer had already benchmarked solutions from a couple of competitors and had determined zones within their office building where the competitors solution would fail. The customer then asked me to demonstrate the to demonstrate my algorithm by placing the client devices in these zones. I was able to demonstrate an almost 2x increase in range with our solution. The shocked look on the faces of the customer was one of the most memorable experiences.

What are you currently working on?

I am currently designing path selection algorithms for hybrid networks that support underlying home networking technologies like WiFi, HomePlug AV, Ethernet etc. This involves determining the best path for a traffic flow between two hybrid devices by monitoring the medium conditions as well as congestion levels on each of the underlying interfaces.

Do your algorithms typically end up in firmware in microcontrollers, or in ASICs or FPGAs?

The PHY algorithms were targeted to hardware implementations. I was involved in all stages of development that included Matlab modeling, design of the fixed point model, RTL implementation and FPGA/ASIC synthesis. In case of the ASIC implementation I had to closely work with the specialist backend team that does the place and route, timing closure.

Note: I cannot comment on the implementation details of the path selection algorithms for hybrid networks.