MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs

MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs


The Mobile Industry Processor Interface (MIPI) is an industry consortium specifying high-speed serial interface solutions to interconnect between components inside a mobile device. The group specifies both protocols and physical layer standards for a variety of applications. The D-PHY is a popular MIPI physical layer standard for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. You can use the CSI-2 interface with D-PHY for the Camera (Imager) to Host interface, as a streaming video interface between devices, and in applications outside of mobile devices.

MIPI D-PHY IP incorporated in the FPGA is able to receive and transmit serial data which consists of one clock and one or more data lanes. The data lanes can switch between the high-speed and low-power signaling through a passive resistor network in unidirectional mode as shown in the following figures. This may be a spate IP block or integrated into the MIPI CSI-2 protocol controllers depending on the IP source or third-party IP partner. The lane control and interface logic are essential to the D-PHY functionality that needs to be built inside the FPGA logic.

The figure above shows the FPGA unidirectional receiver implementation block diagram.

Sources: Intel

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