MultiBoot and Fallback Using ICAP in UltraScale+ FPGAs

MultiBoot and Fallback Using ICAP in UltraScale+ FPGAs


This application note describes a key feature of UltraScale+™ FPGAs—MultiBoot. The MultiBoot feature in UltraScale+ FPGAs allows the FPGA application to load two or more FPGA bitstreams under the control of the FPGA application. The FPGA application triggers a MultiBoot operation, causing the FPGA to reconfigure from a different configuration bitstream. After a MultiBoot operation is triggered, the FPGA restarts its configuration process as usual. This document discusses step-by-step instructions to implement the MultiBoot feature using ICAP, different methods of triggering fallback, and details on how to use the boot status (BOOTSTS) register for debugging and verifying MultiBoot or fallback operation. The application note includes a reference design to demonstrate the MultiBoot capabilities of UltraScale+ FPGAs using ICAP in SPI mode.

The golden image is loaded starting from address location 0 at FPGA power-up. Next, the golden image design triggers a MultiBoot image to be loaded. This step is beneficial when initial system checking is required prior to loading a run time image. The system checking or diagnostics can be contained in the golden image, and the run time operation can be contained in the MultiBoot image. The golden image loaded at power-up triggers booting from an upper address space. Multiple MultiBoot images can exist, and any design can trigger any other image  to be loaded. If an error occurs during loading of the MultiBoot image from the upper address space, the fallback circuitry triggers the golden image to be loaded from address 0x0. The figure shows the flow for the golden image initial setup.

Sources: Xilinx

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