PS and PL-Based Ethernet Performance with LightWeight IP Stack

PS and PL-Based Ethernet Performance with LightWeight IP Stack


This application note provides designs for implementing the PS Ethernet through the EMIO/MIO and Ethernet 1G in the PL to support multiple Ethernet links.

Lightweight IP (lwIP) is an open source TCP/IP networking stack for embedded systems. The Xilinx® software development kit (SDK) provides lwIP software customized to run on the flagship ARM® Cortex®-A53 64-bit quad-core processor or Cortex-R5 32-bit dual-core processor which is a part of the Zynq® UltraScale+™ MPSoC.

This document describes how to use the lwIP library to add networking capability to embedded systems based on the Zynq UltraScale+ MPSoC. The lwIP is used to develop the echo server, web server, trivial file transfer protocol (TFTP) server, and receive and transmit performance test applications. It includes throughput numbers for PS Ethernet, PL Ethernet (1G), and PS-PL Ethernet using gigabyte Ethernet controller (GEM) for lwIP.

The PS-PL Ethernet design is shown in the figure. The GMII interface connects the PHY and PS GEM through the EMIO pins. The GEM0 block is enabled while generating the hardware system in the Vivado® tools.

In the designs described in this application note, the PS-GEM3 is connected to the TI PHY through the reduced gigabit media independent interface (RGMII). This is the default setup for the ZCU102 board. This application note focuses on the design of additional Ethernet ports.

Sources: Xilinx

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