Spartan-7 FPGA Configuration with SPI Flash and Bank 14 at 1.35V

Spartan-7 FPGA Configuration with SPI Flash and Bank 14 at 1.35V


This application note describes a method for configuring a Spartan®-7 FPGA from a 1.8V serial peripheral interface (SPI) NOR flash memory connected to the FPGA dedicated I/O bank 0 at 1.8V and multi-use FPGA I/O bank 14 at 1.35V. This method allows the Spartan-7 FPGA bank 14 to interface to a low-power 1.35V DDR3L memory and low-pin-count SPI configuration storage flash. This mixed, low-voltage configuration is not standard. Thus, data sheet configuration specifications do not apply, and Vivado® design tools do not directly support this configuration. This application note provides the implementation requirements, toolwork-arounds that include a SPI flash programming method, and considerations for thisnon-standard configuration. The relevant FPGA configuration pin connections and descriptions are illustrated in the figure.

Sources: Xilinx

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