## Electronics and Electrical Engineering Design Forum

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Saturday, February 10, 2018 by NYAME EPHRAIM MECHANE

# how can i adjust this logic Diagram to operate in all the above conditions ? When B,C are ON and A off it does not operate

A logic system is required that will sound a buzzer if the conditions within a PCB etching tank are incorrect.  The buzzer must operate if the state of three sensors is as follows:

·                Sensor A is ON and B is ON but C is OFF

·                Sensor A is ON but B and C are both OFF

·                Sensor B is ON but A and C are both OFF

·                Sensors B and C are both ON but A is OFF

Under all other conditions the buzzer must not operate.

Attachment

• To solve this (and similar logic problems) First write out the logic equation

Note: I use * = AND,  + = OR and ~ = NOT for this example

A * B * ~C + A * ~B * ~C + ~A * B * ~C + ~A * B * C

Once you do this you can then use Boolean Algebra to simplify. The site below has an explanation of the rules and steps to take as well as a calculator that you can use to check your answer.
http://electronics-course.com/boolean-algebra

• The problem is that you haven't implemented what's in your truth table.

Let's go through this from the top -- the buzzer will be on if any of the following conditions are met, otherwise it will be off:

#1 Sensor A is ON, B is ON, C is OFF

#2 Sensor A is on, but B and C are both OFF

#3 Sensor B is ON, but A and C are both OFF

#4 Sensors B and C are ON, but A is OFF

Now let's look at the truth table (the one in your attachment) which shows the following:

A B C Q

0 0 0 0
0 0 1 0
0 1 0 1  (#3)
0 1 1 1  (#4)
1 0 0 1  (#2)
1 0 1 0
1 1 0 1  (#1)
1 1 1 0

So far, so good -- this matches up with the text conditions. Now let's use the truth table as a basis for writing the Boolean equations. Note that I use '&' = AND, '|' = OR, and '!' = NOT

#3                           #4                         #2                      #1
Q = (!A & B & !C) | (!A & B & C) | (A & !B & !C) | (A & B & !C)

So now we have to perform standard minimization techniques -- in this case I'd use a Karnaugh map (note that we organize the AB values in such a way as to implement a Gray code).

AB 00 01 11 10
C
0    0    1    1    1
1    0    1    0    0

Since I can't draw on this here, let's gather the 1s into two groups as shown below:

AB 00 01 11 10
C
0    0    *    #    #
1    0    *    0    0

Look at the two '*' characters (these represent (#3 and #4). These say that the output Q is true (1) if A = 0 and B = 1, but we don't care what C is..

We can represent this as W = (!A & B)

Similarly, in the case of the two '#' characters (which represent #1 and #2), these say Q is true (1) if A = 1 and C = 0, but we don't care what B is.

We can represent this as X = (A & !C)

So, our final equation will be Q = W | X

This means we need two NOT gates to give us !A and !C

Then we use an AND gate to give us W = (!A AND B)

And a second AND gate to give us X = (A AND !C)

And an OR gate to give us Q = W OR X

You need to work on making sure you understand this stuff -- once you have these basics out of the way, you'll find everything becomes a lot easier.

Good luck :-)
• NOW you've done it- You've caused Max to write a blog about your question: Truth Tables, Karnaugh Maps, and Logic Gates, Oh My!

Now if we could just figure out how to get him to STOP talking..................

(just kidding!)

-Rick

• @Rick: "...Now if we could just figure out how to get him to STOP talking..."

You should hear my mother -- compared to her I'm an amateur

• @Rick: "...Now if we could just figure out how to get him to STOP talking..."

You should hear my mother -- compared to her I'm an amateur

• From my analysis, there's only one thing wrong with the logic diagram: the inputs are not labeled!   Looking at the Truth Table (or using a Karnaugh Map), the logic function is "q = a&~c | ~a&b".  You can also write it as a multiplexer: "q = a? ~c: b" in Verilog notation.

Now look at the diagram: the only input that's used in both true and complement form is the middle input, so it must be "a".  If "a" is true, the the output is "b", so the top input must be "b".  Similarly, the bottom input must be "c".

IMO there's something else wrong with the logic diagram: I cannot stand OR gates drawn as semi-ellipses instead of arcs that join at a point.  "A trifling matter, and fussy of me, but we all have our little ways." [Eeyore]

• by  Max Maxfield (edited)

@John: "...If you make the middle input "a", the top "b", and the bottom "c", I think the logic works..."

O-M-G... You are correct -- I just assumed the inputs were A, B, C from top to bottom -- so the reason the student couldn't get it working is that he's been applying the wrong stimulus to the circuit.

• by  Max Maxfield (edited)

@John: "...If you make the middle input "a", the top "b", and the bottom "c", I think the logic works..."

O-M-G... You are correct -- I just assumed the inputs were A, B, C from top to bottom -- so the reason the student couldn't get it working is that he's been applying the wrong stimulus to the circuit.