The schematic attached is the circuit I am designing. It is to continuously generate noise at the ADC while there is no signal, and signal+noise when a signal is generated by the DAC. Noise level may be adjustable by R7.
As I have a few components (1DAC, 1ADC, 1op-amp), it is a very basic design. Sorry if I say something wrong because my field of work is not exactly EE.
Common-mode voltage of op-amp is at 1.65V so that DAC varies from 0 to 3.3 while ADC receives from 3.3 to 0, respectively. The inverted value after op-amp will be correct at digital processing after ADC.
I opted noise to come from zener diode, with AC coupled with the C1 (47uF) capacitor that gives high-pass filter with fc=3Hz.
Low-pass filter after DAC has fc=7.2MHz. I intend to generate kind of square wave at DAC, so I am afraid about fc because rising edge of square wave requires high frequency. So, is fc=7.2MHz ok?
R3 and R8 are 10K (high value) but they are not a problem because op-amp input impedance is also too high. Is this ideia correct?
Output current of DAC is at most 1.65/10K = 165uA (output may be negative, i.e., to inside the DAC). Is this alright to DAC MAX5189?
Any positive comment is welcome.